Embodiments of the present invention relate to a superjunction semiconductor device and a method for manufacturing the superjunction semiconductor device. In particular, embodiments of the present invention relate to a superjunction device having a voltage termination structure having a layer of dielectric of an effective thickness.
The success of a controllable semiconductor device at high or ultra-high voltages is almost entirely determined by a successful implementation of the edge termination. Due to the termination of periodic cell structures at the edges of semiconductor devices, high electric fields appear along the edges. Some special arrangements, namely edge termination technologies, are necessary to prevent premature device breakdown along the edges. Field plates, multiple field limiting rings (FLR), semi-insulating polycrystalline silicon (SIPOS) as semi-resistive field plates, silicon etch contours, and beveled p-n junctions are representative edge termination technologies for high voltage semiconductor devices. As the voltage ratings of the semiconductor device increase, the termination region and the ratio between the termination region and the active region often increases. This results in a poorer yield and a higher on-state voltage. In addition, as the voltage ratings of the semiconductor device increase, more elaborate additional process steps for fabrication of the termination are required in order to prevent premature breakdown and to maintain the termination effectiveness.
The invention of superjunction devices by Dr. Xingbi Chen, as disclosed in U.S. Pat. No. 5,216,275, the contents of which are incorporated by reference herein, is a breakthrough and has opened a new scope for the high-voltage semiconductor devices. For example, a 600V superjunction metal-oxide-semiconductor field-effect-transistor (MOSFET) has only about ⅙th-⅛th of the on-state resistance of the conventional power MOSFET. To benefit from the superior performance of superjunction devices, the high-voltage edge termination is inevitable. Improvements to the performance of the superjunction devices may be seen in U.S. Pat. No. 6,410,958 (“Usui, et al.”) and U.S. Pat. No. 6,307,246 (“Nitta, et al.”), both of which are incorporated by reference herein, which show improved voltage breakdown characteristics in superjunction devices.
Prior art superjunction device edge termination designs consume a certain semiconductor area to realize the high breakdown voltage. For example, prior art termination regions typically include multiple field-limiting-rings (FLRs), which are a plurality of outwardly spaced apart doped regions surrounding a peripheral portion of the cell region. An alternate prior art termination region includes a field plate. In both examples, to increase the breakdown voltage in the cell, a greater area must be consumed by either the FLR structure or the field plate. The area consumed by the edge termination region does not contribute to the current-handling-capability of the device (which is determined by the active area size). It has been a goal in the industry to reduce the edge termination size to obtain higher semiconductor wafer output yield. It is desirable to provide an edge termination design that essentially does not consume any portion of the semiconductor wafer/die area.
Additionally, prior art superjunction device edge termination designs typically require a lightly doped epitaxy region (typically n-type, written as n−) in the edge termination region to achieve the high breakdown voltage. The lightly doped epitaxy region has a much lower doping concentration than conductivity regions in the active area (such as the n-columns). Therefore, manufacturers are forced to start with the lightly doped epi-layer or epi-process and convert the epi-layer into higher doped regions in the active area using different doping techniques.
It is desirable to provide an edge termination design without requiring the lightly doped region, thereby permitting the use of a moderately doped epi-layer or epi process and saving half of the doping process for active area formation. It is further desirable to provide a method for manufacturing superjunction devices with such an edge termination region, utilizing known techniques such as plasma etching, reactive ion etching (RIE), inductively coupled plasma (ICP) etching, sputter etching, vapor phase etching, chemical etching, deep RIE, or the like. It is further desirable to provide a method for preventing the premature break down of a superjunction device at the edge portion by using a dielectric termination.